1. Field of the Invention
The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and a semiconductor device manufacturing apparatus, and more particularly, to a chip size package (CSP) sized to a bare chip and a manufacturing method therefor, a manufacturing apparatus therefor.
2. Description of the Related Art
Rapidly Developing CSP techniques, as compared to conventional semiconductor packaging, have produced a reduced package size and weight, high density packaging, and a reduction in manufacturing costs. In particular, three-dimensional and laminate semiconductor devices stacking small-sized semiconductor devices for cellular phones, portable information terminals, notebook computers, digital cameras, and similar equipment, have recently been required for reduction in size and weight.
For instance, Japanese published application JP 08-335663 A discloses a CSP technique which is capable of inspecting with high reliability characteristics and operation state of a bare chip to be packaged. In addition, it discloses that it is possible to stack semiconductor chips having different kinds of carriers without fearing breakage by short circuit to thereby achieve high density packaging in a three-dimensional semiconductor device.
FIG. 1 is a sectional view of a semiconductor device according to a conventional CSP technique. FIG. 2 is a sectional view of a three-dimensional semiconductor device according to the same conventional technique. FIGS. 3 and 4 are sectional views showing a process of secondarily mounting this three-dimensional semiconductor device of the conventional technique to a motherboard. As shown in FIG. 1, a semiconductor device 100 according to this conventional technique (referred to as first prior art) has insulating resin 109 as an adhesive layer placed on the circuit side and side faces of a semiconductor chip 101. The semiconductor chip 101 is surrounded by an interposer substrate 102 composed of a wiring pattern 105 to which an insulating film 110 is adhered on each side, so that the interposer substrate 102 runs along the entire circumference of the semiconductor chip 101. The wiring pattern 105 is connected to a circuit on the front side of the semiconductor chip 101 through a conductor 103. On the rear side of the semiconductor chip 101, which is opposite to the circuit side, the insulating resin 109 is applied to bond the semiconductor chip 101 to the interposer substrate 102. Portions of the interposer substrate 102 that face the circuit side and rear side of the semiconductor chip 101 have a plurality of electrode pads 104 for external connection. A solder bump 107 is formed on each of the electrode pads 104 that face the circuit side of the semiconductor chip 101. The small-sized semiconductor device 100 which has substantially the same size as a bare chip is thus structured in this conventional CSP technique.
The conventional semiconductor device 100 thus formed can be used to build a small-sized, three-dimensional semiconductor device which has substantially the same size as a bare chip by stacking and mounting one semiconductor device 100 and another semiconductor device 100 with the electrode pads 104 and the solder bump 107 sandwiched between them as shown in FIG. 2.
The thus obtained small-sized, three-dimensional semiconductor device which has substantially the same size as a bare chip is secondarily mounted onto a motherboard 111 through the solder bump 107 that faces the circuit side of the lowermost semiconductor device 100 of the stack as shown in FIG. 3. As shown in FIG. 4, underfill resin 108 that is thermosetting resin is inserted between the motherboard 111 and the lowermost semiconductor device 100 of the three-dimensional semiconductor device. The underfill resin 108 seals the solder bump 107 of the lowermost semiconductor device 100. The underfill resin 108 prevents shortening of the life span of the solder bump 107 because of deterioration caused by thermal stress to the solder bump 107 due to the difference in a rate of a linear expansion between the semiconductor chip 101 and the motherboard 111 in variations of temperature. Accordingly, the solder bump 107 is saved from cracking and wire breakage can be avoided.
A Japanese published application JP 2001-196504 A discloses another CSP technique which facilitates manufacturing of a semiconductor device according to the first prior art. FIG. 5 is a sectional view of a semiconductor device 200 according to the CSP technique (referred to as second prior art). FIG. 6 is a sectional view of a three-dimensional semiconductor device according to the second prior art. FIGS. 7 and 8 are sectional views showing a process of secondarily mounting this three-dimensional semiconductor device to a motherboard. As shown in FIG. 5, the semiconductor device 200 according to the second prior art is constituted of a semiconductor chip 101 and a flexible interposer substrate 106 that is composed of a wiring pattern 105 to which thermoplastic insulating resin 112 is adhered on each side. The semiconductor chip 101 is surrounded by the flexible interposer substrate 106 such that the flexible interposer substrate 106 runs along the entire circumference of the semiconductor chip 101. The wiring pattern 105 is connected to a circuit on the front side of the semiconductor chip 101 through a conductor 103 and electrode pads 104. Portions of the flexible interposer substrate 106 that cover the circuit side and rear side of the semiconductor chip 101 have a plurality of electrode pads 104 for external connection. A solder bump 107 is formed on each of the electrode pads 104 that face the rear side of the semiconductor chip 101. In the second prior art, the thermoplastic insulating resin 112 is employed to form the flexible interposer substrate 106. The flexible interposer substrate 106 can therefore readily be adhered to the semiconductor chip 101 by fitting the flexible interposer substrate 106 to the circumferential faces of the semiconductor chip 101 while heating after the flexible interposer substrate 106 is connected to the semiconductor chip 101 through the conductor 103. In addition, bending the flexible interposer substrate 106 along the circumference of the semiconductor chip 101 to bond the two is much easier than in the first prior art because, when heated, the thermoplastic resin 112 is reduced in elastic coefficient and becomes adhesive as well. Moreover, the second prior art does not need the insulating resin 109 inserted as an adhesive layer between the interposer substrate 102 and the semiconductor chip 101 in the first prior art. Therefore manufacturing process and manufacture cost can be reduced for the semiconductor device 102 according to the second prior art.
Similar to the semiconductor device 100 according to the first prior art, the thus formed semiconductor device 200 of the second prior art can be used to build a small-sized, three-dimensional semiconductor device which has substantially the same size as a bare chip. In this case, one semiconductor device 200 and another semiconductor device 200 are stacked and mounted sandwiching the electrode pads 104 and the solder bump 107 between them as shown in FIG. 6.
The thus obtained small-sized, three-dimensional semiconductor device which has substantially the same size as a bare chip is, similar to the three-dimensional semiconductor device according to the first prior art, secondarily mounted onto a motherboard 111 through the solder bump 107 that faces the circuit side of the lowermost semiconductor device 200 of the stack as shown in FIG. 7. As shown in FIG. 8, the underfill resin 108 that is thermosetting resin is inserted between the motherboard 111 and the lowermost semiconductor device 200 of the three-dimensional semiconductor device. The underfill resin 108 seals the solder bump 107 of the lowermost semiconductor device 200 as in the first prior art. Therefore, the underfill resin 108 prevents shortening of the life span of the solder bump 107 because of deterioration caused by thermal stress to the solder bump 107 due to the difference in a rate of linear expansion between the semiconductor chip 101 and the motherboard 111 in variations of temperature. Accordingly, the solder bump 107 is saved from cracking and wire breakage can be avoided.
However, filling the space between the semiconductor device 200 and the motherboard 111 with the underfill resin 108 that is thermosetting resin makes repair impossible if a defect is found in a test to evaluate characteristics of the semiconductor chip 101 and a test for evaluating the quality of the semiconductor device 200 which are conducted after the semiconductor device 200 is secondarily mounted to the motherboard 111. Furthermore, the step of inserting the underfill resin that is thermosetting resin between the semiconductor device and the motherboard substrate and then thermosetting the resin causes an increase in manufacture cost of a semiconductor manufacturing device.